(1) Field of the Invention
The present invention teaches a method of protecting an underlying diffusion barrier layer in a dual damascene trench and via etch process with a coating of negative photoresist, to solve this problem.
(2) Description of Related Art
As a background to the current invention, the damascene processing is a “standard” method for fabricating planar copper interconnects. Damascene wiring interconnects (and/or studs) are formed by depositing a dielectric layer on a planar surface, patterning it using photolithography and oxide reactive ion etch (RIE), then filling the recesses with conductive metal. The excess metal is removed by chemical mechanical polishing (CMP), while the troughs or channels remain filled with metal. For example, damascene wiring lines can be used to form bit lines in DRAM devices, with processing similar to the formation of W studs in the logic and DRAM devices. In both examples, sputtered Ti/TiN liners, underlying diffusion barriers, have been coated with chemical vapor deposited (CVD) W metal, then polished back to oxide.
Chemical vapor deposition (CVD) of W usually requires an underlying conductive diffusion barrier and “seed” layers to prevent consumption of substrate Si from reaction with WF6 at the contact level, and to promote distributed nucleation and low contact resistance. A layer of Ti is used since it provides good adhesion and low contact resistance. However, the Ti alone is not sufficient, because the F from the WF6 reacts with the Ti and produces a brittle, high-resistivity compound. However, the use of a TiN film between the Ti and W solves these problems by enhancing W nucleation while preventing the reaction of F with the Ti or any exposed Si. A W seed layer is then formed an the TiN. More recent processes use a copper seed layer on top of an underlying diffusion barrier (preventing diffusion at both interfaces blocking both copper and silicon diffusion) prior to a copper deposition by electrochemical deposition (ECD). Problems with protecting this underlying diffusion barrier during reactive ion etching (RIE) in the damascene process present some formidable processing challenges.
After conductive metal deposition by electrochemical deposition (ECD) of copper, for example, CMP is applied to complete the inlaid structure. In the CMP process, material is removed from the wafer through the combined effects of a polish pad and an abrasive slurry. The chemical dissolution of material is aided by a mechanical component which is useful in removing passivating surface layers. Chemical and mechanical selectivity's between materials are desired, since CMP must remove the excess metal without removing appreciable amounts of inlaid metal or reducing interconnect thickness.
In the dual-damascene process, a monolithic stud/wire structure is formed from the repeated patterning of a single thick oxide film followed by metal filling and CMP. First, a relatively thick oxide layer is deposited on a planar surface. The oxide thickness is slightly larger than the desired final thickness of the stud and wire, since a small amount of oxide is removed during CMP. Stud recesses are formed in the oxide using photolithography and RIE that either partially etches through the oxide or traverses the oxide and stops on the underlying metal to be contacted. The wire recesses can then be formed using a separate photolithography step and a timed oxide etching step. If the former stud RIE option is used, the wire etching completes the drilling of the stud holes. Problems can exist with protecting this underlying diffusion barrier during reactive ion etching (RIE) in the dual damascene process. For process integration issues, some diffusion barrier layers are deposited and patterned prior the reactive ion etching (RIE) process, in forming the dual damascene structures. Problems with protecting this underlying diffusion barrier during reactive ion etching (RIE) in the dual damascene process present some formidable processing challenges.
Next, the stud/wire metallization is deposited, then planarized using CMP. The resulting interconnects are produced with fewer process steps than with conventional processing and with the dual damascene process, two layer of metal are formed as one, i.e., wiring line and contact stud vias, avoiding an interface between the layers.
Another metal deposition, besides sputtering techniques, has been adapted as a standard for copper metallization. This technique, as mentioned earlier, is electrochemical copper deposition (ECD). It is used for the large grain size (low electromigration) and high deposition rates achieved. The electrochemical copper deposition (ECD) still needs sputtering techniques, physical vapor deposition (PVD), to deposit thin underlying diffusion barrier film (Ta, TaN) and a conductive “seed” layer of copper. As mentioned above, problems with protecting this underlying diffusion barrier during reactive ion etching (RIE) in the dual damascene process presents some formidable processing challenges.
Related patents and relevant literature now follow as Prior Art.
U.S. Pat. No. 5,705,430 entitled “Dual Damascene with a Sacrificial Via Fill” granted Jan. 6, 1998 to Avanzino et al. describes a dual damascene process with a sacrificial fill layer in the via opening. A dual damascene method of fabricating is described for interconnection level of conducting lines and connecting vias separated by insulation, for building integrated circuits with semiconductor devices, using a sacrificial via fill.
U.S. Pat. No. 5,635,423 Patent entitled “Simplified Dual Damascene Process for Multi-Level Metallization and Interconnection Structure” granted Jun. 3, 1997 to Huang et al. teaches a dual damascene process with a trench etch followed by a via etch. A semiconductor device containing an interconnect structure having a reduced interwiring spacing is produced by this modified dual damascene process, which uses an etch stop layer. The trench and via formed by this process are simultaneously filled with conductive metal.
U.S. Pat. No. 5,933,761 Patent entitled “Dual Damascene Structure and Its Manufacturing Method” granted Aug. 3, 1999 to Lee describes a dual damascene process with etch stops. The invention uses two ion implantation steps to form two etch stop layers. It uses the stop layers to perform an anisotropic etching step to form via and trench structures. Another feature reported is the use of a device sidewall spacer as a trench mask, instead of a multi-mask process, thereby preventing mask misalignment.
U.S. Pat. No. 5,801,099 Patent entitled “Method for Forming Interconnection of Semiconductor Device” granted Sep. 1, 1998 to Kim et al. describes a modified dual damascene process with a conductive plug filling the via opening. First and second trench regions are formed and filled with conductive material, thereby forming an upper conductive line.